RT-TOOLS accepted papers

Regular papers

Karine Altisen, INRIA Rhône-Alpes, France and Stavros Tripakis, IMAG Grenoble, France
Tools for controller synthesis of timed systems

Gilles Audemard, Alessandro Cimatti, Artur Kornilowicz, and Roberto Sebastiani; ITC-irst, Italy
Bounded model checking for timed systems

Béatrice Bérard, ENS Cachan, France; Patricia Bouyer, Aalborg U, Denmark; and Antoine Petit, ENS Cachan, France
Analysing the PGM protocol with uppaal

Dragan Bosnacki, Eindhoven U of Techn., The Netherlands
Partial order and symmetry reductions for discrete time

Martin Carlsson, Enea OSE Systems AB, Sweden; Jakob Engblom, IAR Systems AB, Sweden; Andreas Ermedahl, Uppsala U, Sweden; Jan Lindblad, Enea OSE Systems AB, Sweden; and Björn Lisper, Mälardalen U, Sweden
Worst-case execution time analysis of disable interrupt regions in a commercial real-time operating system

Anton Cervin, Dan Henriksson, Bo Lincoln, and Karl-Erik Årzén; Lund Inst. of Techn., Sweden
Jitterbug and TrueTime: Analysis tools for real-time control systems

Alexandre David, Uppsala U, Sweden; Gerd Behrmann, Aalborg U, Denmark; Kim Guldstrand Larsen, Aalborg U, Denmark; and Wang Yi, Uppsala U, Sweden
New uppaal architecture

Goran Frehse, U Dortmund, Germany
Solving simulation relations of timed automata for the design and verification of timed discrete controllers

Robert P. Goldman, Smart Information Flow Technologies, USA; Michael J. S. Pelican, Honeywell, USA; and David J. Musliner, Honeywell, USA
Verifier trace-directed backjumping for controller synthesis

Jesper Møller, IT U of Copenhagen, Denmark
Simplifying fixpoint computations in verification of real-time systems